The present invention relates in general to data processing systems, and in particular, to the execution of load and store instructions in a processor.
Aliasing occurs when a Real Address (RA) may be mapped to multiple Effective Addresses (EA). This is the case in certain architectures where bits 50 and 51 of the EA always translate to bits 50 and 51 of the RA. Therefore, there might be four EAs that can map to the same RA.
Because it is an error in such architecture to store more than one cache line at two different EAs which map to the same RA, the herein disclosed structure of the Real Address Tag addresses the problem by invalidating the previously stored cache line to make room for the next line at the new EA. Bits 50 and 51 of the EA are used to select between 4 sub-arrays (for each set) in the RA Tag which contain the RA the current EA maps into. During a cycle in which a new EA is mapped to a RA (through the ERAT or some other Effective to Real address translation mechanism), the RA Tag looks up the new RA and compares it with the RAs already stored in its 4 sub-arrays. If a match occurs, then a different EA already maps to the RA and the cache line at the old EA location must be invalidated. This is known as an Alias Hit.
In order to invalidate the cache line, the RA Tag sends a xe2x80x9c1 hotxe2x80x9d signal to other logic blocks (Cache, Tag, ERAT, etc.) specifying which EA the Alias Hit was detected for. Since bits 50 and 51 of the EA were used for storing the RA, the RA Tag simply needs to send a 4-bit field to the other logic blocks to inform them which line to clear. For example, if sub-array 0 hits then bits 50 and 51 of the EA must have been 00, and the 4 bit field is 0001, if sub-array 1 hits then bits 50 and 51 of the EA must have been 01 and the 4 bit field is 0010, etc.
Encoding the bits in this way (known as 2B encoding) makes it easier for the other logic blocks to decode the location and thus improve access time. The arrays simply need to perform logical ANDing of bits for the number of address bits minus 1. For instance, if the address is 2 bits wide, the encoding would be 0001, 0010, 0100, 1000. The active bits would map directly to the wordline addresses. If the address is 3 bits wide then the encoding would be 00010001, 00010010, 00010100, etc. And only a 2 input logical AND is necessary to map to the correct wordline. When all bits are xe2x80x980xe2x80x99 then no wordlines are being selected.
If a failure occurs within the RA Tag or in some other logic block which controls it, there might be a case in which more than one Alias Hit is detected. This should be flagged as a failure, since the job of the RA Tag is to avoid multiple Aliasing altogether. Therefore, there is a need for a solution for detecting such failures.
The present invention addresses the foregoing need by utilizing the Alias Hit signals to detect errors within the RA tag arrays. More specifically, an error is reported if more than one Alias Hit signal is received from a set of RA tag arrays, or if more than one Alias Hit signal is received from more than one set of RA tag arrays.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.